Code Generation Techniques for Irregular Architectures

The fast development of many different ASIPs make demands of rapid availability of dedicated compilers. Fast retargeting is a major aspect, while fast compilation times are of minor importance. There are also new demands in the quality of the generated code. Irregular properties together with fine–grain parallelism given by a target architecture have to be effectively supported by the compiler. This report is focused on the traditional tasks of code generation — code selection, register allocation, and instruction scheduling. The major subject is to expose the tendencies of research of code generation techniques in recent years, and survey their features with regards to support for irregular architectures, fine–grain parallelism, retargetability, and phase coupling. The report outlines the preferable techniques involved in code generators. Features of irregular architectures being sufficiently supported by these techniques are examined. The insufficiencies with regards to irregular architectures are described and approaches to overcome them are described. The essential problems arising are due to mutual dependencies among the tasks of code generation. Thus, phase ordering problems and phase coupling approaches are a very important issue of the report. Retargeting is discussed with regards to retargetability of the described techniques, but also with regards to the quality of the generated code. Relations of structural and behavioral models are exposed, addressing the issue of supporting both, the design process of the target architecture and effective retargeting of all tasks of code generation.